A memory component such as a storage drive typically has nonvolatile storage memory also referred to as persistent storage memory, which retains data stored in the memory notwithstanding a power loss to the storage drive. Nonvolatile storage memory may also be packaged in memory modules such as dual-inline memory modules (DIMM), for example.
The capacity of such nonvolatile storage memory continues to grow. For example, Intel's three dimensional (3D) quad level cell (QLC) NAND memory has a capacity of 128 Gigabytes (GB). As such, the need to reduce the amount of time needed to write data to the memory, that is, “program” the memory, is growing as well. The process of writing data to the memory typically includes an initial data input phase or interval in which the memory component inputs a set of data such as a page of data, for example, which has been output by a processor or other external controller, and then programs in a programming interval, a bitcell array of the memory component with the page of inputted data. Thus, the total time to input and program write data in the memory component may be the sum of the data input interval and the data program interval.
One approach to reducing write data process time is to program the bitcell array with one page (the “current” page) of previously input data while at the same time, caching the next page of input data in internal latches or registers in anticipation of the next data programming interval. Thus, the programming interval of the current page of data overlaps with the data input and caching interval of the next page of data. In some nonvolatile storage memory, the bitcell array may be programmed faster than the time needed to input and cache the next page of input data. As a result, the total write process time for each page of data is reduced to the data input and caching interval. Such an approach may improve overall performance of the memory component by as much as 30% in some cases.
In one known design, a solid state drive has a cache register or latch which latches a page of write data from an external processor or controller. The page of write data is then transferred to a write data register prior to programming the bitcell array with the page of write data. The next page of write data may be cached in the cache register while the first page of write data is written to the array. A solid state drive may have several such data registers for a variety of purposes. For example, in multiple level cells (MLC) having multiple bits per bitcell, the solid state drive may have multiple write data registers (such as five, for example, in a quad level cell (QLC)) to support programming MLC bitcells.
In some nonvolatile memory components, a failure in the programming interval of a page of data may lead to loss of some or all of that page of data in the memory component. One approach to avoiding such data loss in the memory component is to retain a copy of the page of data in an external volatile memory cache such as dynamic random access memory (DRAM) until the page of data is successfully programmed into the nonvolatile storage memory component. Thus, if the programming interval of a page of data fails in the nonvolatile storage memory component causing loss of the page of data within the nonvolatile storage memory component, the page of data may nonetheless be successfully retrieved from the external volatile memory cache. Another approach is to apply an Exclusive-OR process to reconstruct data lost due to a programming interval failure. The data is reconstructed by performing multiple read and read retry operations directed to the bitcell array and processing the read data with Exclusive-OR functions.